WebPHY                         A Web Interface for FPGAs


Why put a web server in a FPGA?

Command/Control/Data Interface
Most FPGA applications require some sort of error-free command/control interface.  A web interface offers error-free data transfer over TCP/IP in both directions, suitable for use as a command/control interface.

Graphical User Inferface
Typically, controlling an FPGA via a GUI requries platform-specific software (MAC, Linux, Windows) to be written on a computer to communicate with the FPGA.  A web server is essentially a built-in GUI that lives inside the FPGA.

Internet Connectivity
A web server allows connection of an FPGA directly to the internet via a router, which can then be accessed and controlled from anywhere in the world via tablet, smartphone or PC.

Platform Independence
A web server is platform independant; web browsers running on Windows, Linux, Mac OS and Android all load and run the same HTML and JavaScript code served by your web server.

Why use WebPHY DATABUS over a soft-CPU solution?

Lower FPGA utilization
An equivalent soft-CPU solution requires up to 4x as many LUTs, FFs and BRAMs.  The WebPHY DATABUS core fits in even the smallest (xc6lx4) Spartan-6 FPGA consuming only 20% of its flip flops and 50% of its LUTs.

Less external hardware

No external Flash, DRAM, or Ethernet PHY chips are required.  The WebPHY DATABUS core is completely self-contained and requires only a few passive components to connect to an Ethernet mag-jack via LVDS IO.

Simpler to use and maintain

Soft-CPU web server solutions require a software development environment, toolchain and software TCP/IP stack to be integrated, tested and maintained along with the existing HDL environment.  WebPHY DATABUS simply drops into an FPGA and is ready to use in minutes without any CPU or software environment.

How is the web page customized?

The user maintains the core's web page as one or more web files, such as .html, .css, and .js.  The included romgen script concatenates and compresses the web files into a single initialized BRAM .vhdl file and a .txt upload file.  The BRAM .vhdl file is instantiated in the user's design and connected to the core.  The .txt upload file is used with the core's Live Update feature to allow instant upload of user web page modifications to the core's web page BRAM.
How is user data transferred between the core and the client?

The core receives HTTP POST messages containing either "rd" or "wr" commands from the client.  These commands allow specified lengths of bytes to be transferred to and from the user's 32 bit address space.

How do I use MATLAB/Octave to transfer data to the core?

The following example shows how the urlread() command can be used in either MATLAB or Octave to read/write data to the WebPHY DATABUS core:

% IP address of FPGA

fpga_ip = "";

% Write 8 bytes to BRAM address 0x1002 and read them back.

s = urlread (strcat(fpga_ip,'wr_0x1002_0x0123456789ABCDEF'),'p

s = urlread (strcat(fpga_ip,'rd_0x1002_0x8'),'post',{'',''});

fprintf('read 0x%s from FPGA\n',s);

% Move servo motor and write to 7 segment display.

s = urlread (strcat(fpga_ip,'wr_0x0_0x1234'),'post',{'',''});

You can try this code with our live online demo FPGA.  Just click the Live Demo link to log onto our online demo, get the resolved IP address and set it to fpga_ip in the code above.  Run the code to write a value, read it back, and move the servo motor to position 0x1234.