WebPHY                         A Web Interface for FPGAs
Interactive Demos



image/svg+xml This demo is hosted on a Digilent Spartan-3 FPGA evaluation board A simple RC bias circuit converts LVDS to 10Base-TX signalling for PHY-less operation RJ45 Mag-jack connects to a router for internect connectivity RJ45 Mag-jack connects to a router for internect connectivity Activity LED LVDS TX+ LVDS_TX- LVDS TX- LVDS_RX+ LVDS RX+ LVDS_RX- LVDS RX- bus signals (wr, wr_dat[7:0], rd, rd_ack, rd_dat[7:0], addr[31:0]) bus signals The DATABUS core connects to Ethernet via LVDS and acts as a bus master WebPHY DATABUS IP Core The DATABUS core connects to Ethernet via LVDS and acts as a bus master DATABUS™ IPCore WebPHY A 16-bit register mapped to address 0x0 commands the servo motor using a PWM signal The Servo peripheral uses a 16-bit register to control the position of a servo motor Servo Peripheral 7-segment peripheral is mapped to same address as servo peripheral and displays the commanded position 7-segment peripheral is mapped to same address as servo peripheral and displays the commanded position 7-Seg LED Peripheral bus signals (wr, wr_dat[7:0], rd, rd_ack, rd_dat[7:0], addr[31:0]) bus signals bus signals (wr, wr_dat[7:0], rd, rd_ack, rd_dat[7:0], addr[31:0]) bus signals LVDS RX- LVDS RX- LVDS RX- LVDS RX- LVDS RX- LVDS RX- LVDS RX- The code running in the browser is stored in Block RAM on the FPGA, including the WebScope JavaScript application. The code running in the browser is stored in Block RAM on the FPGA, including the WebScope JavaScript application. Web Page BRAM
IO Control
Move a servo and toggle LEDs using GPIO, Servo and Display peripherals for the WebPHY DATABUS IP core



image/svg+xml This demo is hosted on a Digilent Spartan-3 FPGA evaluation board A simple RC bias circuit converts LVDS to 10Base-TX signalling for PHY-less operation RJ45 Mag-jack connects to a router for internect connectivity RJ45 Mag-jack connects to a router for internect connectivity Activity LED LVDS TX+ LVDS_TX- LVDS TX- LVDS_RX+ LVDS RX+ LVDS_RX- LVDS RX- The DATABUS core connects to Ethernet via LVDS and acts as a bus master WebPHY DATABUS IP Core The DATABUS core connects to Ethernet via LVDS and acts as a bus master DATABUS™ IPCore WebPHY A 9-bit counter connected to WebScope A simple 9-bit counter connected to WebScope Counter The WebScope Logic Analyzer peripheral communicates through the DATABUS core to the WebScope JavaScript application running in the browser. In this example, it monitors a counter, ADC interface and bus signals. The WebScope Logic Analyzer peripheral communicates through the DATABUS core to the corresponding WebScope JavaScript application running on the browser WebScope™ Peripheral SPI signals from an ADC interface connected to WebScope ADC I/F bus signals The code running in the browser is stored in Block RAM on the FPGA, including the WebScope JavaScript application. The code running in the browser is stored in Block RAM on the FPGA, including the WebScope JavaScript application. Web Page BRAM
FPGA Debugging
Trigger, capture and view live waveforms from a counter, ADC interface and bus signals running on a Spartan-3 FPGA using the WebScope Logic Analyzer peripheral for the WebPHY DATABUS IP core